Power MOS devices, including lateral diffused MOS (LDMOS) devices, are employed in a variety of applications, such as, for example, power amplifiers in wireless communications systems. Radio frequency (RF) LDMOS devices are generally fabricated on a semiconductor wafer comprising a substrate that is typically formed of single crystal silicon which has been heavily doped with an impurity, such as, for example, boron, so as to form a low-resistivity substrate (e.g., about 1018 to about 1019 atoms per cubic centimeter). A lightly doped epitaxial layer (e.g., about 1014 to about 1015 atoms per cubic centimeter), typically about ten microns thick, is generally formed on the substrate.
One problem in fabricating the LDMOS device is providing a low-resistance electrical path from the device formed near an upper surface of the wafer, through the lightly-doped epitaxial layer to the more heavily-doped substrate below. Previous attempts to solve this problem typically involve forming a diffused sinker by doping the surface of the silicon with a heavy boron predeposition or implanting a relatively high dose ion implant, which is then driven at a high temperature (e.g., in excess of 1000 degrees Celsius) for a long duration (e.g., typically in excess of about 10 hours) through the epitaxial layer and down to the substrate. In driving the diffusion or implant down into the silicon, however, the dopant will out-diffuse on either side by a certain amount, typically about 8 microns. Thus, the formation of the diffused sinker consumes a substantially large area in the wafer. The requirement of a high-dose implant step can also result in excessive implant time for the wafer as well as unacceptable wafer heating.
The long period of time required for the high temperature drive-in process can undesirably result in a large up-diffusion of dopant from the heavily-doped substrate into the lightly-doped epitaxial layer which effectively thins the epitaxial layer, thereby lowering the junction breakdown voltage and increasing junction leakage. Additionally, an increase in the number of misfit dislocations can occur, generally originating from mismatches between the lattices of the epitaxial layer and substrate, from the epitaxial layer/substrate interface to the surface of the epitaxial layer. This often leads to reliability problems, among other disadvantages.
Other known attempts at providing a low-resistance path between the upper surface of the wafer and the substrate below have involved forming one or more conductive plugs in the epitaxial layer down to the substrate. This methodology involves first forming trenches (e.g., by a dry etching process) or v-grooves (e.g., by a wet etching process) through the epitaxial layer down to the substrate and depositing a conductive material, such as, for example, tungsten, metal or silicide, in the trenches or v-grooves, thereby establishing an electrical connection with the substrate. A primary disadvantage of this approach, however, is the inability to control a surface doping in the substrate and source silicon to produce acceptable contact resistance between the substrate/source silicon and deposited conductive layer. Another disadvantage with this approach is the need to precisely control the fill of the trench so as to ensure a substantially planar surface, which is essential for further processing, and a substantially void-free fill, typically a requirement in forming a sufficiently low-resistance contact.
There exists a need, therefore, for an enhanced substrate contact capable of improved performance and reliability that does not suffer from one or more of the above-noted deficiencies typically affecting conventional substrate contacts. Furthermore, it would be desirable if such a substrate contact was fully compatible with a conventional semiconductor process technology.